Details
ASIC Design and Verification Course Contents
ASIC Design Flow
Netlist Generation
ASIC verification
Backend Design Flow of ASIC
Analysis of Backend Design parameter
Essential Level SOC designing
Digital Subsystem Design and Verification
Implementation and Timing Closure of Digital IC’s
Designing for programmable VLSI systems Live Project
- Fundamentals of AMS IC Design
- Fundamentals of Analog Circuit Design
- Fundamentals of Logic Design
- Designing using Verilog, Linux & Tcl
- ASIC Design Flow
- RTL Designing
- Constraints Designing
- STA analysis
- Essential Level DFT
- Advanced RTL Design using Verilog
- RTL Verification using Verilog
- Design Synthesis for ASIC methodologies
- Full custom
- Automatic Place and Route concepts for Functional blocks
- Full chip IC’s for various package types and IR drop specs
- Programmable VLSI architectures
- HDL techniques for high performance designs intended for programmable logic devices
- Optimization and timing analysis techniques
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